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| integrated silicon solution, inc. 1 rev. j 07/15/2010 is61lf25672a is61vf25672a is61lf51236a is61vf51236a is61lf102418a is61vf102418a copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fail ure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. prod ucts are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances features ? internal self-timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and control ? burst sequence control using mode input ? three chip enable option for simple depth expan- sion and address pipelining ? common data inputs and data outputs ? auto power-down during deselect ? single cycle deselect ? snooze mode for reduced-power standby ? jtag boundary scan for pbga package ? power supply lf: v dd 3.3v + 5%, v ddq 3.3v/2.5v + 5% vf: v dd 2.5v + 5%, v ddq 2.5v + 5% ? jedec 100-pin tqfp, 119-pin pbga, 209-ball pbga and 165-pin pbga packages. ? lead-free available july 2010 256k x 72, 512k x 36, 1024k x 18 18mb synchronous flow-through static ram description the issi is61lf/vf25672a, is61lf/vf51236a and is61lf/vf102418a are high-speed, low-power synchro- nous static rams designed to provide burstable, high- performance memory for communication and networking applications. the is61lf/vf25672a is organized as 262,144 words by 72 bits. the is61lf/vf51236a is orga- nized as 524,288 words by 36 bits. the is61lf/vf102418a is organized as 1,048,576 words by 18 bits. fabricated with issi 's advanced cmos technology, the device inte- grates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic cir- cuit. all synchronous inputs pass through registers con- trolled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. byte write operation is performed by using byte write enable ( bwe ) input combined with one or more individual byte write signals ( bwx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the adv (burst address ad- vance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. fast access time symbol parameter -6.5 -7.5 units t kq clock access time 6.5 7.5 ns t kc cycle time 7.5 8.5 ns frequency 133 117 mhz
2 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a block diagram 19/20 binary counter gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 17/18 19/20 address register ce d clk q dq(a-d) byte write registers d clk q enable register ce d clk q bwe bw(a-h) x18: a,b x36: a-d x72: a-h ce ce2 ce2 256kx72; 512kx36; 1024kx18; memory array 36,18 or 72 input registers clk oe 2/4/8 oe dqa - dqd 36,18 or 72 36,18 or 72 a power down zz integrated silicon solution, inc. 3 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a bottom view bottom view 165-pin bga 165-ball, 13x15 mm bga 119-pin bga 119-ball, 14x22 mm bga bottom view 209-ball bga 209-ball, 14 mm x 22 mm bga 1 mm ball pitch, 11 x 19 ball array 4 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a pin configuration ? 256k x 72, 209-ball pbga (top view) 1234567891011 a dqg dqg a ce2 adsp adsc adv ce2 a dqb dqb b dqg dqg bw c bw gnc bwe a bw b bw f dqb dqb c dqg dqg bw h bw dnc ce nc bw e bw a dqb dqb d dqg dqg vss nc nc oe gw nc vss dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb f dqc dqc vss vss vss nc vss vss vss dqf dqf g dqc dqc v ddq v ddq v dd nc v dd v ddq v ddq dqf dqf h dqc dqc vss vss vss nc vss vss vss dqf dqf j dqc dqc v ddq v ddq v dd nc v dd v ddq v ddq dqf dqf k nc nc clk nc vss nc vss nc nc nc nc l dqh dqh v ddq v ddq v dd nc v dd v ddq v ddq dqa dqa m dqh dqh vss vss vss nc vss vss vss dqa dqa n dqh dqh v ddq v ddq v dd nc v dd v ddq v ddq dqa dqa p dqh dqh vss vss vss zz vss vss vss dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd vss nc nc mode nc nc vss dqe dqe u dqd dqd nc a a a a a nc dqe dqe v dqd dqd a a a a1 a a a dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe 11 x 19 ball bga?14 x 22 mm 2 body?1 mm ball pitch pin descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce , ce2 , ce2 synchronous chip select bw x (x=a,b,c,d synchronous byte write e,f,g,h) controls symbol pin name bwe byte write enable oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqx data inputs/outputs dqpx data inputs/outputs v dd 3.3v/2.5v power supply v ddq isolated output power supply 3.3v /2.5v vss ground integrated silicon solution, inc. 5 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 119 bga package pin configuration- 512k x 36 (top view) 123456 7 a v ddq aa adsp aav ddq b nc a a adsc a a nc c nc a a v dd a a nc d dqc dqpc vss nc vss dqpb dqb e dqc dqc vss ce vss dqb dqb f v ddq dqc vss oe vss dqb v ddq g dqc dqc bwc adv bwb dqb dqb h dqc dqc vss gw vss dqb dqb j v ddq v dd nc v dd nc v dd v ddq k dqd dqd vss clk vss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ddq dqd vss bwe vss dqa v ddq n dqd dqd vss a 1 * vss dqa dqa p dqd dqpd vss a 0 * vss dqpa dqa r nc a mode v dd nc a nc t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq note: * a 0 and a 1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. pin descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance. adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce synchronous chip select bw x (x=a-d) synchronous byte write controls bwe byte write enable symbol pin name oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqd data inputs/outputs dqpa-pd data inputs/outputs v dd power supply v ddq output power supply vss ground 6 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 119 bga package pin configuration 1m x 18 (top view) note: * a 0 and a 1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. 123456 7 a v ddq aa adsp aa v ddq b nc a a adsc a a nc c nc a a v dd a a nc d dqb nc vss nc vss dqpa nc e nc dqb vss ce vss nc dqa f v ddq nc vss oe vss dqa v ddq g nc dqb bwb adv vss nc dqa h dqb nc vss gw vss dqa nc j v ddq v dd nc v dd nc v dd v ddq k nc dqb vss clk vss nc dqa l dqb nc vss nc bwa dqa nc m v ddq dqb vss bwe vss nc v ddq n dqb nc vss a 1 * vss dqa nc p nc dqpb vss a 0 * vss nc dqa r nc a mode v dd nc a nc t nc a a nc a a zz u v ddq tms tdi tck tdo nc v ddq pin descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance. adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce synchronous chip select bw x (x=a,b) synchronous byte write controls bwe byte write enable symbol pin name oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqb data inputs/outputs dqpa-pb data inputs/outputs v dd power supply v ddq output power supply vss ground integrated silicon solution, inc. 7 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a note: * a 0 and a 1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. 1234567891011 a nc a ce bwc bwb ce2 bwe adsc adv anc b nc a ce2 bwd bwa clk gw oe adsp anc c dqpc nc v ddq vss vss vss vss vss v ddq nc dqpb d dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb e dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb f dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb g dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb h nc vss nc v dd vss vss vss v dd nc nc zz j dqd dqd v ddq v dd vss vss vss v dd v ddq dqa dqa k dqd dqd v ddq v dd vss vss vss v dd v ddq dqa dqa l dqd dqd v ddq v dd vss vss vss v dd v ddq dqa dqa m dqd dqd v ddq v dd vss vss vss v dd v ddq dqa dqa n dqpd nc v ddq vss nc a vss vss v ddq nc dqpa p nc nc a a tdi a 1 * tdo a a a a r mode nc a a tms a 0 * tck a a a a 165 pbga package pin configuration 512k x 36 (top view) pin descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance. adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce , ce2 , ce2 synchronous chip select bw x (x=a,b,c,d) synchronous byte write controls symbol pin name bwe byte write enable oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqd data inputs/outputs dqpa-pd data inputs/outputs v dd power supply v ddq output power supply vss ground 8 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a note: * a 0 and a 1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. 165 pbga package pin configuration 1m x 18 (top view) 1234567891011 a nc a ce bwb nc ce2 bwe adsc adv aa b nc a ce2 nc bwa clk gw oe adsp anc c nc nc v ddq vss vss vss vss vss v ddq nc dqpa d nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa e nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa f nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa g nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa h nc vss nc v dd vss vss vss v dd nc nc zz j dqb nc v ddq v dd vss vss vss v dd v ddq dqa nc k dqb nc v ddq v dd vss vss vss v dd v ddq dqa nc l dqb nc v ddq v dd vss vss vss v dd v ddq dqa nc m dqb nc v ddq v dd vss vss vss v dd v ddq dqa nc n dqpb nc v ddq vss nc a vss vss v ddq nc nc p nc nc a a tdi a 1 * tdo a a a a r mode nc a a tms a 0 * tck a a a a pin descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance. adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce , ce2 , ce2 synchronous chip select bw x (x=a,b) synchronous byte write controls symbol pin name bwe byte write enable oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqd data inputs/outputs dqpa-pd data inputs/outputs v dd power supply v ddq output power supply vss ground integrated silicon solution, inc. 9 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a pin configuration dqpb dqb dqb vddq vss dqb dqb dqb dqb vss vddq dqb dqb vss nc vdd zz dqa dqa vddq vss dqa dqa dqa dqa vss vddq dqa dqa dqpa a a ce ce2 bwd bwc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a dqpc dqc dqc vddq vss dqc dqc dqc dqc vss vddq dqc dqc nc vdd nc vss dqd dqd vddq vss dqd dqd dqd dqd vss vddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss vdd a a a a a a a a a 46 47 48 49 50 512k x 36 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable ce , ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqd synchronous data input/output dqpa-dqpd parity data input/output vss ground gw synchronous global write enable mode burst sequence mode selection oe output enable tms, tdi, jtag boundary scan pins tck, tdo v dd 3.3v/2.5v power supply v ddq isolated output buffer supply: 3.3v/2.5v zz snooze enable 10 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a a nc nc vddq vss nc dqpa dqa dqa vss vddq dqa dqa vss nc vdd zz dqa dqa vddq vss dqa dqa nc nc vss vddq nc nc nc a a ce ce2 nc nc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a nc nc nc vddq vss nc nc dqb dqb vss vddq dqb dqb nc vdd nc vss dqb dqb vddq vss dqb dqb dqpb nc vss vddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss vdd a a a a a a a a a 46 47 48 49 50 pin configuration 1024k x 18 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwb synchronous byte write enable bwe synchronous byte write enable ce , ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqb synchronous data input/output dqpa-dqpb parity data i/o; dqpa is parity for dqa1-8; dqpb is parity for dqb1-8 v ss ground gw synchronous global write enable mode burst sequence mode selection oe output enable tms, tdi, jtag boundary scan pins tck, tdo v dd 3.3v/2.5v power supply v ddq isolated output buffer supply: 3.3v/2.5v zz snooze enable integrated silicon solution, inc. 11 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a truth table (1-8) (3ce option) operation address ce ce ce ce ce ce2 ce2 ce2 ce2 ce2 ce2 zz adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe clk dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l xxxxl-h high-z deselect cycle, power-down none l h x l l xxxxl-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h xxxxxx high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l hhhhll-h q read cycle, suspend burst current x x x l hhhhhl-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x hhhhl-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d note: 1. x means ?don?t care.? h means logic high. l means logic low. 2. for write , l means one or more byte write enable signals ( bwa-h ) and bwe are low or gw is low. write = h for all bwx , bwe , gw high. 3. bwa enables writes to dqa?s and dqpa. bwb enables writes to dqb?s and dqpb. bwc enables writes to dqc?s and dqpc. bwd enables writes to dqd?s and dqpd. bwe enables writes to dqe?s and dqpe. bwf enables writes to dqf?s and dqpf. bwg enables writes to dqg?s and dqpg. bwh enables writes to dqh?s and dqph. dqpa-dqph are available on the x72 version. dqpa and dqpb are available on the x18 version. dqpa-dqpd are available on the x36 version. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. see write timing diagram for clarification. 12 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a truth table (1-8) (1ce option) next cycle address ce ce ce ce ce adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe dq deselected none h x l x x x high-z read, begin burst external l l x x x l q read, begin burst external l l x x x h high-z write, begin burst external l h l x l x d read, begin burst external l h l x h l q read, begin burst external l h l x h h high-z read, continue burst next x h h l h l q read, continue burst next x h h l h h high-z read, continue burst next h x h l h l q read, continue burst next h x h l h h high-z write, continue burst next x h h l l x d write, continue burst next h x h l l x d read, suspend burst current x h h h h l q read, suspend burst current x h hhhh high-z read, suspend burst current h x h h h l q read, suspend burst current h x hhhh high-z write, suspend burst current x h h h l x d write, suspend burst current h x h h l x d note: 1. x means ?don?t care.? h means logic high. l means logic low. 2. for write , l means one or more byte write enable signals ( bwa-h ) and bwe are low or gw is low. write = h for all bwx , bwe , gw high. 3. bwa enables writes to dqa?s and dqpa. bwb enables writes to dqb?s and dqpb. bwc enables writes to dqc?s and dqpc. bwd enables writes to dqd?s and dqpd. bwe enables writes to dqe?s and dqpe. bwf enables writes to dqf?s and dqpf. bwg enables writes to dqg?s and dqpg. bwh enables writes to dqh?s and dqph. dqpa-dqph are available on the x72 version. dqpa and dqpb are available on the x18 version. dqpa-dqpd are available on the x36 version. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. see write timing diagram for clarification. partial truth table function gw gw gw gw gw bwe bwe bwe bwe bwe bwa bwa bwa bwa bwa bwb bwb bwb bwb bwb bwc bwc bwc bwc bwc bwd bwd bwd bwd bwd bwe bwe bwe bwe bwe bwf bwf bwf bwf bwf bwg bwg bwg bwg bwg bwh bwh bwh bwh bwh read h h x x x x x x x x read h l h h h h h h h h write byte 1 h l l h h h h h h h write all bytes h l l l l l l l l l write all bytes l x x x x x x x x x integrated silicon solution, inc. 13 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a interleaved burst address table (mode = v dd or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = vss) 0,0 1,0 0,1 a1', a0' = 1,1 absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to vss for i/o pins ?0.5 to v ddq + 0.5 v v in voltage relative to vss for ?0.5 to v dd + 0.5 v for address and control inputs v dd voltage on v dd supply relative to vss ?0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 14 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a power supply characteristics (1) (over operating range) 6.5 7.5 max max symbol parameter test conditions temp. range x18 x36 x72 x18 x36 uni t i cc ac operating device selected, com. 250 250 300 240 240 ma supply current oe = v ih , zz v il , ind. 275 275 350 250 250 all inputs 0.2v or v dd ? 0.2v, cycle time t kc min. i sb standby current device deselected, com. 140 140 140 140 140 ma ttl input v dd = max., ind. 150 150 150 150 150 all inputs v il or v ih , zz v il , f = max. i sbi standby current device deselected, com. 110 110 110 110 110 ma cmos input v dd = max., ind. 125 125 125 125 125 v in v ss + 0.2v or v dd ? 0.2v f = 0 i sb 2 sleep mode zz>v ih com. 60 60 60 60 60 ma ind. 75 75 75 75 75 note: 1. mode pin has an internal pullup and should be tied to v dd or v ss . it exhibits 100 a maximum leakage current when tied to v ss + 0.2v or v dd ? 0.2v. dc electrical characteristics (over operating range) 3.3v 2.5v symbol parameter test conditions min. max. min. max. unit v oh output high voltage i oh = ?4.0 ma (3.3v) 2.4 ? 2.0 ? v i oh = ?1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) ? 0.4 ? 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 v v il input low voltage ?0.3 0.8 ?0.3 0.7 v i li input leakage current v ss v in v dd (1) ?5 5 ?5 5 a i lo output leakage current v ss v out v ddq , oe = v ih ?5 5 ?5 5 a operating range (is61lfxxxxx) range ambient temperature v dd v ddq commercial 0c to +70c 3.3v 5% 3.3v/2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v/2.5v 5% operating range (is61vfxxxxx) range ambient temperature v dd v ddq commercial 0c to +70c 2.5v 5% 2.5v 5% industrial -40c to +85c 2.5v 5% 2.5v 5% note: 1. v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested. integrated silicon solution, inc. 15 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac test loads figure 2 317 5 pf including jig and scope 351 output 3.3v figure 1 output z o = 50 1.5v 50 16 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 1.25v 50 output 1,667 5 pf including jig and scope 1,538 output +2.5v figure 3 figure 4 2.5v i/o output load equivalent integrated silicon solution, inc. 17 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a read/write cycle switching characteristics (1) (over operating range) 6.5 7.5 symbol parameter min. max. min. max. unit fmax clock frequency ? 133 ? 117 mhz t kc cycle time 7.5 ? 8.5 ? ns t kh clock high time 2.2 ? 2.5 ? ns t kl clock low time 2.2 ? 2.5 ? ns t kq clock access time ? 6.5 ? 7.5 ns t kqx (2) clock high to output invalid 2.5 ? 2.5 ? ns t kqlz (2,3) clock high to output low-z 2.5 ? 2.5 ? ns t kqhz (2,3) clock high to output high-z ? 3.8 ? 4.0 ns t oeq output enable to output valid ? 3.2 ? 3.4 ns t oelz (2,3) output enable to output low-z 0 ? 0 ? ns t oehz (2,3) output disable to output high-z ? 3.5 ? 3.5 ns t as address setup time 1.5 ? 1.5 ? ns t ws read/write setup time 1.5 ? 1.5 ? ns t ces chip enable setup time 1.5 ? 1.5 ? ns t avs address advance setup time 1.5 ? 1.5 ? ns t ds data setup time 1.5 ? 1.5 ? ns t ah address hold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? ns t dh data hold time 0.5 ? 0.5 ? ns t pds zz high to power down ? 2 ? 2 cyc t pus zz low to power down ? 2 ? 2 cyc notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2. 18 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a read/write cycle timing single read flow-through single write high-z high-z data out data in oe ce2 ce2 ce bwd-bwa bwe gw address adv adsc adsp clk rd1 wr1 wr1 1a 1a 2a 2b 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh adsp is blocked by ce inactive t ss t sh t as t ah t ws t wh t ws t wh t ws t wh rd2 rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeqx t kq t oehz t kqx t kqhz t ds t dh t kqhz t kqlz high-z t kqlz t kq integrated silicon solution, inc. 19 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a write cycle timing single write data out data in oe ce2 ce2 ce bwd-bwa bwe gw address adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce1 inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a 20 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a snooze mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z snooze mode electrical characteristics symbol parameter conditions min. max. unit i sb 2 current during snooze mode zz vih ? 60 ma t pds zz active to input ignored ? 2 cycle t pus zz inactive to input sampled 2 ? cycle t zzi zz active to snooze current ? 2 cycle t rzzi zz inactive to exit snooze current 0 ? ns integrated silicon solution, inc. 21 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a ieee 1149.1 serial boundary scan (jtag) the is61lf/vf51236a and is61lf/vf102418a have a serial boundary scan test access port (tap) in the pbga package only. this port operates in accordance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant taps. the tap operates using jedec stan- dard 2.5v i/o logic levels. disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (vss) to prevent clocking of the device. tdi and tms are internally pulled up and may be disconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left disconnected. on power-up, the de- vice will start in a reset state which will not interfere with the device operation. test access port (tap) - test clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any register. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms tap controller block diagram 22 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the in- struction register. this register is loaded when it is placed between the tdi and tdo pins. (see tap controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (vss) when the bypass instruction is ex- ecuted. boundary scan register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample-z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded to the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has vendor code and other information described in the identification register definitions table. scan register sizes register name bit size bit size bit size (x18) (x36) (x72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan 75 75 tbd identification register definitions instruction field description 256kx72 512k x 36 1m x 18 revision number (31:28) reserved for versi on number. xxxx xxxx xxxx device depth (27:23) defines depth of sram. 512k or 1m 00110 00111 01000 device width (22:18) defines with of the sram. x36 or x18 00101 00100 00011 issi device id (17:12) reserved for future use. xxxxx xxxxx xxxxx issi jedec id (11:1) allows unique identification of sram vendor. 00011010101 00011010101 00011010101 id register presence (0) indicate the presence of an id register. 1 1 1 integrated silicon solution, inc. 23 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a tap instruction set eight instructions are possible with the three-bit instruction register and all combinations are listed in the instruction code table. three instructions are listed as reserved and should not be used and the other five instructions are described below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals and cannot preload the input or output buffers. the sram does not implement the 1149.1 com- mands extest or intest or the preload portion of sample/preload ; instead it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed be- tween tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. because extest is not implemented in the tap controller, this device is not 1149.1 standard compliant. the tap controller recognizes an all-0 instruction. when an extest instruction is loaded into the instruction regis- ter, the sram responds as if a sample/preload instruction has been loaded. there is a difference between the instructions, unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample-z the sample-z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not imple- mented, so the tap controller is not fully 1149.1 compli- ant. when the sample/preload instruction is loaded to the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock operates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. be- cause of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under- go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabi- lized long enough to meet the tap controller?s capture set- up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/preload instruction. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk and clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it short- ens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions. 24 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a instruction codes code instruction description 000 extest captures the input/output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. 001 idcode loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. 010 sample-z captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. 011 reserved do not use: this instruction is reserved for future use. 100 sample/preload captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 reserved do not use: this instruction is reserved for future use. 110 reserved do not use: this instruction is reserved for future use. 111 bypass places the bypass register between tdi and tdo. this operation does not affect sram operation. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10 tap controller state diagram integrated silicon solution, inc. 25 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a tap electrical characteristics over the operating range (1,2) symbol parameter test conditions min. max. units v oh1 output high voltage i oh = ?2.0 ma 1.7 ? v v oh2 output high voltage i oh = ?100 a 2.1 ? v v ol1 output low voltage i ol = 2.0 ma ? 0.7 v v ol2 output low voltage i ol = 100 a ? 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage i olt = 2ma ?0.3 0.7 v i x input load current vss v i v ddq ?5 5 ma notes: 1. all voltage referenced to ground. 2. overshoot: v ih (ac) v dd +1.5v for t t tcyc /2, undershoot: vil (ac) 0.5v for t t tcyc /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms. tap ac electrical characteristics (1,2) (over operating range) symbol parameter min. max. unit t tcyc tck clock cycle time 100 ? ns f tf tck clock frequency ? 10 mhz t th tck clock high 40 ? ns t tl tck clock low 40 ? ns t tmss tms setup to tck clock rise 10 ? ns t tdis tdi setup to tck clock rise 10 ? ns t cs capture setup to tck rise 10 ? ns t tmsh tms hold after tck clock rise 10 ? ns t tdih tdi hold after clock rise 10 ? ns t ch capture hold after clock rise 10 ? ns t tdov tck low to tdo valid ? 20 ns t tdox tck low to tdo invalid 0 ? ns notes: 1. both t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. 26 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a don't care undefined tck tms tdi tdo t thtl t tlth t thth t mvth t thmx t dvth t thdx 1 2 3 4 5 6 t tlox t tlov tap timing 20 pf tdo gnd 50 1.25v/1.5v z 0 = 50 tap output load equivalent tap ac test conditions input pulse levels 0 to 2.5v/0 to 3.0v input rise and fall times 1ns input timing reference levels 1.25v/1.5v output reference levels 1.25v/1.5v test load termination supply voltage 1.25v/1.5v integrated silicon solution, inc. 27 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 165 pbga boundary scan order (512k x 36) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 mode 1r 21 dqb 11g 41 nc 1a 61 dqd 1j 2 a 6n 22 dqb 11f 42 ce 2 6a 62 dqd 1k 3 a 11p 23 dqb 11e 43 bw a 5b 63 dqd 1l 4 a 8p 24 dqb 11d 44 bw b 5a 64 dqd 1m 5 a 8r 25 dqb 10g 45 bw c 4a 65 dqd 2j 6 a 9r 26 dqb 10f 46 bw d 4b 66 dqd 2k 7 a 9p 27 dqb 10e 47 ce2 3b 67 dqd 2l 8 a 10p 28 dqb 10d 48 ce 3a 68 dqd 2m 9 a 10r 29 dqb 11c 49 a 2a 69 dqd 1n 10 a 11r 30 nc 11a 50 a 2b 70 a 3p 11 zz 11h 31 a 10a 51 nc 1b 71 a 3r 12 dqa 11n 32 a 10b 52 dqc 1c 72 a 4r 13 dqa 11m 33 adv 9a 53 dqc 1d 73 a 4p 14 dqa 11l 34 adsp 9b 54 dqc 1e 74 a1 6p 15 dqa 11k 35 adsc 8a 55 dqc 1f 75 a0 6r 16 dqa 11j 36 oe 8b 56 dqc 1g 17 dqa 10m 37 bwe 7a 57 dqc 2d 18 dqa 10l 38 gw 7b 58 dqc 2e 19 dqa 10k 39 clk 6b 59 dqc 2f 20 dqa 10j 40 nc 11b 60 dqc 2g 28 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 165 pbga boundary scan order (1m x 18) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 mode 1r 21 dqa 11g 41 nc 1a 61 dqb 1j 2 a 6n 22 dqa 11f 42 ce 2 6a 62 dqb 1k 3 a 11p 23 dqa 11e 43 bw a 5b 63 dqb 1l 4 a 8p 24 dqa 11d 44 nc 5a 64 dqb 1m 5 a 8r 25 dqa 11c 45 bw b 4a 65 dqb 1n 6 a 9r 26 nc 10f 46 nc 4b 66 nc 2k 7 a 9p 27 nc 10e 47 ce2 3b 67 nc 2l 8 a 10p 28 nc 10d 48 ce 3a 68 nc 2m 9 a 10r 29 nc 10g 49 a 2a 69 nc 2j 10 a 11r 30 a 11a 50 a 2b 70 a 3p 11 zz 11h 31 a 10a 51 nc 1b 71 a 3r 12 nc 11n 32 a 10b 52 nc 1c 72 a 4r 13 nc 11m 33 adv 9a 53 nc 1d 73 a 4p 14 nc 11l 34 adsp 9b 54 nc 1e 74 a1 6p 15 nc 11k 35 adsc 8a 55 nc 1f 75 a0 6r 16 nc 11j 36 oe 8b 56 nc 1g 17 dqa 10m 37 bwe 7a 57 dqb 2d 18 dqa 10l 38 gw 7b 58 dqb 2e 19 dqa 10k 39 clk 6b 59 dqb 2f 20 dqa 10j 40 nc 11b 60 dqb 2g integrated silicon solution, inc. 29 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 209 boundary scan order (256k x 72) 30 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a ordering information (v dd = 3.3v/v ddq = 2.5v/3.3v) commercial range: 0c to +70c configuration access time order part number package 256kx72 6.5 is61lf25672a-6.5b1 209 pbga 512kx36 6.5 is61lf51236a-6.5tq 100 tqfp is61lf51236a-6.5b2 119 pbga is61lf51236a-6.5b3 165 pbga 512kx36 7.5 is61lf51236a-7.5tq 100 tqfp is61lf51236a-7.5b2 119 pbga is61lf51236a-7.5b3 165 pbga 1mx18 6.5 is61lf102418a-6.5tq 100 tqfp is61lf102418a-6.5tql 100 tqfp, lead-free is61lf102418a-6.5b2 119 pbga is61lf102418a-6.5b3 165 pbga 1mx18 7.5 is61lf102418a-7.5tq 100 tqfp is61lf102418a-7.5b2 119 pbga is61lf102418a-7.5b3 165 pbga industrial range: -40c to +85c configuration access time order part number package 256kx72 6.5 is61lf25672a-6.5b1i 209 pbga 512kx36 6.5 is61lf51236a-6.5tqi 100 tqfp is61lf51236a-6.5b2i 119 pbga is61lf51236a-6.5b2li 119 pbga, lead-free is61lf51236a-6.5b3i 165 pbga 512kx36 7.5 is61lf51236a-7.5tqi 100 tqfp is61lf51236a-7.5tqli 100 tqfp, lead-free is61lf51236a-7.5b2i 119 pbga is61lf51236a-7.5b3i 165 pbga is61lf51236a-7.5b3li 165 pbga, lead-free 1mx18 6.5 is61lf102418a-6.5tqi 100 tqfp is61lf102418a-6.5b2i 119 pbga is61lf102418a-6.5b3i 165 pbga 1mx18 7.5 is61lf102418a-7.5tqi 100 tqfp is61lf102418a-7.5tqli 100 tqfp, lead-free is61lf102418a-7.5b2i 119 pbga is61lf102418a-7.5b3i 165 pbga is61lf102418a-7.5b3li 165 pbga, lead-free integrated silicon solution, inc. 31 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a ordering information (v dd = 2.5v /v ddq = 2.5v) commercial range: 0c to +70c configuration access time order part number package 256kx72 6.5 is61vf25672a-6.5b1 209 pbga 512kx36 6.5 is61vf51236a-6.5tq 100 tqfp is61vf51236a-6.5b2 119 pbga is61vf51236a-6.5b3 165 pbga 512kx36 7.5 is61vf51236a-7.5tq 100 tqfp is61vf51236a-7.5b2 119 pbga is61vf51236a-7.5b3 165 pbga 1mx18 6.5 is61vf102418a-6.5tq 100 tqfp is61vf102418a-6.5b2 119 pbga is61vf102418a-6.5b3 165 pbga 1mx18 7.5 is61vf102418a-7.5tq 100 tqfp is61vf102418a-7.5b2 119 pbga is61vf102418a-7.5b3 165 pbga industrial range: -40c to +85c configuration access time order part number package 256kx72 6.5 is61vf25672a-6.5b1i 209 pbga 512kx36 6.5 is61vf51236a-6.5tqi 100 tqfp is61vf51236a-6.5b2i 119 pbga is61vf51236a-6.5b3i 165 pbga 512kx36 7.5 is61vf51236a-7.5tqi 100 tqfp is61vf51236a-7.5tqli 100 tqfp, lead-free is61vf51236a-7.5b2i 119 pbga is61vf51236a-7.5b3i 165 pbga 1mx18 6.5 is61vf102418a-6.5tqi 100 tqfp is61vf102418a-6.5b2i 119 pbga is61vf102418a-6.5b3i 165 pbga 1mx18 7.5 is61vf102418a-7.5tqi 100 tqfp is61vf102418a-7.5b2i 119 pbga is61vf102418a-7.5b3i 165 pbga 32 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 1. controlling dimension : mm note : package outline 12/10/2007 integrated silicon solution, inc. 33 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 34 integrated silicon solution, inc. rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 1. controlling dimension : mm . note : 2. reference document : jedec ms-028 10/02/2008 package outline integrated silicon solution, inc. 35 rev. j 07/15/2010 is61lf25672a is61lf51236a is61lf102418a is61vf25672a is61vf51236a is61vf102418a 1. controlling dimension : mm . note : package outline 08/28/2008 |
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